Selected Works
Verilog Stopwatch
Stopwatch made in Verilog with highly accurate timekeeping capabilities, including complex pause, resume, and reset functionalities.
Verilog
Digital System Design
Hardware Simulation
Synchronous FIFO
Implementation and exploration of a Synchronous FIFO along with comprehensive Verilog testbench techniques to guarantee signal integrity across hardware states.
Verilog
Testbenches
Clock Domains
Upcoming
8086 Implementation
A deep dive into computer architecture, building an implementation aligned with the Intel 8086 microprocessor instruction set and fetching pipeline.
Microprocessors
Assembly
Architecture
Upcoming
Audio Isolation & Enhancement
A ground-up built audio filter leveraging fundamental concepts of signals and systems to isolate specific frequencies and enhance audio clarity.
Signals & Systems
DSP
MATLAB